Freescale Semiconductor /MK60DZ10 /VREF /SC

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SC

7 43 0 0 00 0 0 0 0 0 0 0 0 (00)MODE_LV 0 (0)VREFST 0 (0)REGEN 0 (0)VREFEN

REGEN=0, VREFST=0, VREFEN=0, MODE_LV=00

Description

VREF Status and Control Register

Fields

MODE_LV

Buffer Mode selection

0 (00): Bandgap on only, for stabilization and startup

2 (10): Tight-regulation buffer enabled

VREFST

Internal Voltage Reference has settled

0 (0): The bandgap is disabled or not ready.

1 (1): The bandgap is ready.

REGEN

Regulator enable

0 (0): Internal 1.75 V regulator is disabled.

1 (1): Internal 1.75 V regulator is enabled.

VREFEN

Internal Voltage Reference enable

0 (0): The module is disabled.

1 (1): The module is enabled.

Links

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